Bit Error Rate of the VDC at 80 Mbit/s

 
 
 
 
 

Measurements:

The VDC (VCSEL Driver Chip) was tested at higher speeds as designed for. A bit rate of 80 Mbits/sec could be needed for a similar circuitry for the ATLAS Pixel Detector instead of 40 Mbits/sec as in the SCT.

A first ,,quick and dirty" test was done with a pulse generator and an optical receiver (the so-called Rudge Receiver). A VDC was supplied with 8-bit-bursts within 32 bits. The light signal from the VCSEL was sent to the receiver, which transforms optical signals into digital (LVDS) and analog signals. The analog and digital signals were observed with an oscilloscope in infinite persistence mode. A bit error-rate of about 1 x10-6 would be visible on the scope. But no errors appeared (figure 1).

Figure 1: Hardcopy of an infinite persistence (30 min) shot taken at 80Mbit/sec with an 8bit burst in 32 bit. The upper signal is the digital output of the receiver, the lower the analog output.
 



Figure 2: Hardcopy of an infinite persistence (8 hours) shot taken at 240 Mbit/sec with an 8 bit burst within 32 bit. The signal is the analog output of the receiver.




This was repeated at an even higher bit rate. Figure 2 shows a hardcopy of the analog signal (Rudge Receiver) taken at 240 Mbits/sec over a time of 8 hours. The same test was done with an optical probe (Tektronix 6709 1GHz) and the result is shown in figure 3.


Figure 3:Hardcopy of 120 MHz signal. The light signal was captured with an optical probe.

These results led to the setting up of an experiment to measure the BER of this system at 80Mbits/sec. Figure 3 shows the schematic of this set-up. The pulse generator was triggered from an external system to send an 8 bit burst within 32 bits. The output was set to LVDS levels (1.0 V low and 1.4 V high).


Figure 4: Schematic of the experimental set-up




The signals were received by the VDC, which supplied the VCSEL with approx. 15mA. The light signals received by the Rudge Receiver were attenuated with a 5dB attenuator since this receiver was originally designed for LED signals.

The digital output of the receiver (LVDS) was compared with the delayed original signal using a XOR. The output was sent through a discriminator because edge jitter of the two signals produced spikes in the output of the XOR which were counted by as errors. The discriminator threshold was set to a value that was between the spike height and the level of genuine errors.

This experiment ran for 17 hours at the weekend and 2 errors occurred. This hives an estimated BER of 8 x 10-13 . This takes into account the fact the data was not random.

Conclusions:

 The VDC/VCSEL has been tested at a data rate of 80 Mbits/s. No rise in the BER was observed.

                                                                  BER = 8 x 10-13
 
 

Comments please mail to:  I.M. Gregor 

 

 
 
 

last modified : 28 May 1999